The present application is related to and co-filed with to the U.S. application Ser. No. 13/789,681 entitled “Gilbert Mixer with Negative gm to Increase NMOS Mixer Conversion” filed on Mar. 8, 2011 which is assigned to the same assignee as the present application and incorporated herein by reference in its entirety and the present application is related to the U.S. application Ser. No. 13/312,820 entitled “Injection Locked Divider with Injection Point Located at a Tapped Inductor” filed on Dec. 6, 2011 which is assigned to the same assignee as the present application and invented by the same inventor as the present application and incorporated herein by reference in its entirety and Ser. No. 13/442,387 entitled “Method and Apparatus of Transceiver Calibration Using Substrate Coupling” filed on Apr. 9, 2012, which is assigned to the same assignee as the present application and incorporated herein by reference in its entirety.
Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS). Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. At 60 GHz, a divider of a clock signal providing a 30 GHz is an important building block. Another important consideration is locking or syncing the on-chip oscillator to a second independent clock signal.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel devices and P-channel devices (MOS device) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS devices. Current channel lengths are 40 nm, the power supply of VDD equals 1.2V and the number of layers of metal levels can be 8 or more.
Oscillator and frequency dividers are elements in communication systems. The highest performance circuits in a given technology are usually measured in some form of an on-chip free running oscillator, such as a ring oscillator using transistors or a resonant oscillator that uses transistors and reactive components in a regenerative connection. Once these clocks are generated on-chip, a Phase Lock Loop (PLL) can be used to control the frequency of operation as is well known in the art.
Direct conversion transceiver mixes an oscillator frequency with a baseband signal to generate a carrier frequency of the signal which is substantially identical to the oscillator frequency. This modulation is called up-conversion. A particular problem in direct conversion is frequency pulling and locking of a first clock signal from an on-chip oscillator due to a second clock signal with a frequency close to that of the on-chip oscillator. This is known as clock injection. This second independent clock signal can lock and shift the frequency of operation of the first clock signal away from the design parameters. An injection locked on-chip oscillator has a range of frequencies that the oscillator will lock on to (the locking range) In addition, the locking can be a problem in direct conversion transmitters.
High frequency signals as used in WiGig transceivers have carrier frequencies around 60 GHz. In addition, parasitic capacitance plays an influential role in the performance of electrical circuits The drain/gate capacitance is about 10 fF per micron width while the wire used to interconnect the drain to the inductor can have an inductance of 1 pH/μm. In particular, this parasitic capacitance can degrade the operation of on-chip clock oscillators, which are typically the components on a chip that achieve the highest frequency capabilities. In addition, the skin effect causes resistive losses as the length of the interconnect increases.
The injection of the second clock signal into the oscillator of the first clock signal can occur through the substrate conductance or through free space by inductive and/or capacitive coupling. One apparent technique would be separating the oscillator from the source of the second signal by using distance. However, as mentioned earlier, at 60 GHz, the parasitic inductance, capacitance and resistance of the increased interconnect length degrades the performance of the transceiver.